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cy7c603xx encore? iii low voltage cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-16018 rev. *l revised february 23, 2011 encore? iii low voltage features powerful harvard-architecture processor ? m8c processor speeds to 12 mhz ? low power at high speed ? 2.4 v to 3.6 v operating voltage ? operating voltages down to 1.0 v using on-chip switch mode pump (smp) ? commercial temperature range: 0 c to +70 c configurable peripherals ? 8-bit timers, counters, and pwm ? full duplex master or slave spi ? 10-bit adc ? 8-bit successive approximation adc ? comparator flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 512 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer?) ? full-featured, in-circuit emulator and programmer ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 2.5% 24 and 48 mhz oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 10 ma drive on all general purpose io (gpio) ? pull-up, pull-down, high-z, st rong, or open drain drive modes on all gpio ? up to 8 analog inputs on gpio ? configurable interrupt on all gpio versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations additional system resources ? i 2 c master, slave, and multimaster to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference applications wireless mice wireless gamepads wireless presenter tools wireless keypads playstation ? 2 wired gamepads playstation 2 bridges for wireless gamepads ? applications requiring a cost effective low voltage 8-bit microcontroller. digital system sram 512 bytes system bus interrupt controller clock sources (includes imo and ilo) global digital interconnect global analog interconnect cpu core (m8c) srom flash 8k system resources analog system analog ref. digital clocks i2c por and lvd system resets internal voltage ref. switch mode pump port 1 port 0 sleep and watchdog analog mux port 3 port 2 analog psoc block array digital psoc block array encore iii lv core logic block diagram [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 2 of 39 contents encore iii low voltage functional overview ................ 3 encore iii lv core ..................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 3 additional system resources ..................................... 4 encore iii lv device characteristics ............................. 4 getting started .................................................................. 4 development kits ........................................................ 4 development tools .......................................................... 5 psoc designer software subsyst ems .......... .............. 5 in-circuit emulator ....................................................... 5 designing with psoc designer ....................................... 6 select components ..................................................... 6 configure components .......... .............. .............. ......... 6 organize and connect .............. .............. ........... ......... 6 generate, verify, and debug ....................................... 6 pin information ................................................................. 7 28-pin part pinout ........................................................ 7 32-pin part pinout ........................................................ 8 register reference ......................................................... 11 register conventions ................................................ 11 register mapping tables .......................................... 11 electrical specifications ................................................ 15 absolute maximum ratings ... .................................... 16 operating temperature ............................................. 16 dc electrical characteristics ..................................... 17 ac electrical characteristics ..................................... 22 packaging information ................................................... 28 packaging dimensions .............................................. 28 thermal impedances ................................................ 30 solder reflow peak temperat ure ............................. 30 ordering information ...................................................... 31 ordering code definitions ..... .................................... 31 acronyms ........................................................................ 32 acronyms used ......................................................... 32 reference documents .................................................... 32 document conventions ................................................. 33 units of measure ....................................................... 33 numeric conventions ............ .................................... 33 glossary .......................................................................... 33 document history page ................................................. 38 sales, solutions, and legal information ...................... 39 worldwide sales and design s upport ......... .............. 39 products .................................................................... 39 psoc? solutions ...................................................... 39 [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 3 of 39 encore iii low voltage functional overview the encore iii low voltage (encore iii lv) cy7c603xx device is based on the flexible psoc ? architecture. this supports a simple set of peripherals that can be configured to match the needs of each application. additionally, a fast cpu, flash program memory, sram data memo ry, and configurable io are included in a range of convenient pinouts. this architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. a fast cpu, flash program memory, sram data memory, and configurable io are included in both 28-pin ssop and 32-pin qfn packages. the encore iii lv architecture, as shown in figure 1 , consists of four main areas: the enc ore iii lv core, the system resources, digital system, and analog system. configurable global bus resources allow combining all the device resources into a complete custom system . each encore iii lv device supports a limited set of digital and analog peripherals. depending on the package, up to 28 general purpose ios (gpios) are also included. the gpios provide access to the global digital and analog interconnects. encore iii lv core the encore iii lv core is a powerful engine that supports a rich feature set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low-speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 12 mhz. the m8c is a four mips 8-bit harvard -architecture microprocessor. the core includes a cpu, memory, clocks, and configurable gpio (general purpose io). system resources provide additional capability, such as digital clocks to increase flexibility, i 2 c functionality for implementing an i 2 c master, slave, multi-master, an internal voltage reference that provides an absolute valu e of 1.3 v to a number of subsystems, a switch mode pump (smp) that generates normal operating voltages off a single battery cell, a nd various system resets supported by the m8c. the digital system the digital system consists of 4 digital encore iii lv blocks. each block is an 8-bit resource. digital peripheral configurations include the following: pwm usable as timer or counter spi master and slave i2c slave and multi-master cmp adc10 saradc figure 1. digital system block diagram the digital blocks may be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. the analog system the analog system consists of two configurable blocks. analog peripherals are very flexible and may be customized to support specific application requiremen ts. some of the common analog functions for this device (available as user modules) are: analog-to-digital converters (single with 8-bit resolution) pin-to-pin comparators single-ended comparators with absolute (1.3 v) reference 1.3 v reference (as a system resource) analog blocks are provided in columns of two, which includes one ct (continuous time - ace00 or ace01) and one sc (switched capacitor - ase10 or ase11) blocks. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital encore iii lv block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 3 port 2 port 1 port 0 [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 4 of 39 figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analo g system for analysis with comparators and analog-to-digital converters. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. additional system resources system resources, some of wh ich are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a switch mode pump, low voltage detection, and power on reset. brief statements describing the merits of each system resource follow. digital clock dividers provide three customizable clock frequencies for use in applications. th e clocks can be routed to both the digital and analog systems. addi tional clocks may be generated using di gital blocks as clock dividers. the i 2 c module provides 100 khz and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection interrupts can signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system. an integrated switch mode pu mp generates normal operating voltages from a single 1.2 v battery cell, providing a low-cost boost converter. versatile analog mu ltiplexer system. encore iii lv device characteristics the encore iii lv devices have four digital blocks and four analog blocks. table 1 lists the resources available for specific encore iii lv devices. getting started the quickest path to understanding the encore iii lv silicon is by reading this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an overview of the encore iii lv and presents specific pin, register, and electrical specifications. encore iii lv is based on the architecture of the cy8c21x34. for in-depth information, along with detailed programming information, refer to the psoc programmable system-on-chip technical reference manual, which is available at http://www.cypress.com . for up-to-date ordering, packaging, and electrical specification information, refer to the latest device data sheets on the web at http://www.cypress.com . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for encore iii lv development. go to the cypress online store web site at http://www.cypress.com . acol1mux ace00 ace01 array array input configuration ase10 ase11 x x x x x analog mux bus all io aci0[1:0] aci1[1:0] table 1. encore iii lv device characteristics part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy7c60323- pvxc 24 1 4 24 0 2 4 512 bytes 8k [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 5 of 39 development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp or windows vista. this system provides design database management by project, an integrated debug ger with in-circuit emulator, in-system programming support, and built -in support for third-party assemblers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view a drag-and-drop visual embedded system design environment based on psoc express. in the syst em-level view you create a model of your system inputs, outputs, and communication interfaces. you define when and how an output device changes state based upon any or all ot her system devices. based upon the design, psoc designer automatically selects one or more psoc mixed-signal controllers that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide). choose a base device to work with and then select different onboard analog and digital components called user modules that use the pso c blocks. examples of user modules are adcs, dacs, amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configuration enables changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules and routing, and generate code. then switch to the chip-level view to gain complete control over on-chip resources. all views of the project share a common code editor, builder, and common deb ug, emulation, and programming tools. code generation tools psoc designer supports multiple third party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers enable assembly code to merge seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products enable you to create complete c progra ms for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an inter nal view of the psoc device. debugger commands enable the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and st ep control. the debugger also enables the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low-cost, high functionality in-cir cuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24-mhz) operation. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 6 of 39 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components both the system-level and chip-l evel views provide a library of prebuilt, pretested hardware peripheral components. in the system-level view, these components are called drivers and correspond to inputs (a thermistor, for example), outputs (a brushless dc fan, for example), communication interfaces (i 2 c-bus, for example), and the logic to control how they interact with one another (called valuators). in the chip-level view, the components are called user modules. user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that en able you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the pa rameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. both the system-level drivers an d chip-level user modules are documented in datasheets that are viewed directly in psoc designer. these datasheets explain the internal operation of the component and provide performance specifications. each datasheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. organize and connect you can build signal chains at the chip level by interconnecting user modules to each other and the i/o pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. in the system-level view, sele cting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (pga) to buffer the input from the potentiometer, an analog-to-digital converter (adc) to convert the potentiometer?s output to a digital signal, and a pwm to control the fan. in the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the generate application step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the software for the system. both system-level and chip-lev el designs generate software based on your design. the chip-level design provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. the system-level design also generates a c ma in() program that completely controls the chosen application and contains placeholders for custom code at strategic positions . this allows you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger subsystem. the debugger downloads the hex image to the ic e where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the d ebugger provides a large trace buffer and allows you define complex breakpoint events. these include monitoring address and data bus values, memory locations and external signals. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 7 of 39 pin information the encore iii lv device is available in 28-pin ssop and 32-p in qfn packages. every port pin (labeled with a ?p?) is capable of digital io and connection to the common analog bus. however, vss, vdd, smp, and xres are not capable of digital io. 28-pin part pinout figure 3. cy7c60323-pvxc 28-pin device a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] vss m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 table 2. pin definitions - cy7c60323-pvxc 28-pin device pin no. type name description digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input and column output. 3 io i, m p0[3] analog column mux input and column output, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 io m p2[7] 6 io m p2[5] 7 io i, m p2[3] direct switched capacitor block input. 8 io i, m p2[1] direct switched capacitor block input. 9 power vss ground connection. 10 io m p1[7] i 2 c serial clock (scl). 11 io m p1[5] i 2 c serial data (sda). 12 io m p1[3] 13 io m p1[1] i 2 c serial clock (scl), issp-sclk. 14 power vss ground connection. 15 io m p1[0] i 2 c serial data (sda), issp-sdata. 16 io m p1[2] 17 io m p1[4] optional external clock input (extclk). 18 io m p1[6] 19 input xres active high external reset with internal pull down. 20 io i, m p2[0] direct switched capacitor block input. 21 io i, m p2[2] direct switched capacitor block input. 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input 25 io i, m p0[2] analog column mux input 26 io i, m p0[4] analog column mux input 27 io i, m p0[6] analog column mux input 28 power vdd supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 8 of 39 32-pin part pinout a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 4. cy7c60323-lfxc 32-pin device a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] smp qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 5. cy7c60333-lfxc 32-pin device [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 9 of 39 a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 6. cy7c60323-ltxc 32-pin device sawn a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] smp qfn 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 7. cy7c60333-ltxc 32-pin device sawn [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 10 of 39 table 3. 32-pin part pinout (qfn [1] ) pin no. type name description digital analog 1 io i, m p0[1] analog column mux input, integrating input. 2 io m p2[7] 3 io m p2[5] 4 io m p2[3] 5 io m p2[1] 6 io m p3[3] in cy7c60323 part. 6 power smp switch mode pump (smp) connection to required external components in cy7c60333 part. 7 io m p3[1] in cy7c60323 part. 7 power vss ground connection in cy7c60333 part. 8 io m p1[7] i 2 c serial clock (scl). 9 io m p1[5] i 2 c serial data (sda). 10 io m p1[3] 11 io m p1[1] i 2 c serial clock (scl), issp-sclk. 12 power vss ground connection. 13 io m p1[0] i 2 c serial data (sda), issp-sdata. 14 io m p1[2] 15 io m p1[4] optional external clock input (extclk). 16 io m p1[6] 17 input xres active high external re set with internal pull-down. 18 io m p3[0] 19 io m p3[2] 20 io m p2[0] 21 io m p2[2] 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input. 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. 29 io i, m p0[7] analog column mux input. 30 io i, m p0[5] analog column mux input 31 io i, m p0[3] analog column mux input, integrating input. 32 power vss ground connection. legend a = analog, i = input, o = output, and m = analog mux input. note 1. the qfn package has a center pad that must be connected to ground (vss). [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 11 of 39 register reference this section lists the registers of the encore iii lv device. for detailed register information, refer the psoc system-on-chip technical reference manual . register conventions the register conventions specific to this section are listed in ta b l e 4 . register mapping tables the encore iii lv device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set to 1 the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 4. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific table 5. register map 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 cur_pp d0 rw 11 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 12 of 39 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 5. register map 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 13 of 39 table 6. register map 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 14 of 39 dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 6. register map 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 15 of 39 electrical specifications this section presents the dc and ac electric al specifications of the encore iii lv dev ice. for up-to-date electrical specificati ons, check the latest data sheet by visiting the web at http://www.cypress.com . specifications are valid for 0 c ? t a ? 70 c and t j ? 85 c as specified, except where noted. refer to table 19 on page 22 for the electrical specifications for the inte rnal main oscillator (imo) using slimo mode. figure 10. voltage versus cpu frequency figure 11. imo frequency trim options the allowable cpu operating region for 12 mhz has been extended down to 2.7 v from the original 3.0 v design target. the custom er?s application is responsible for monitoring voltage and throttling back cpu speed in accordance with figure 10 when voltage approaches 2.7 v. refer to table 16 for lvd specifications. note that the device does not support a preset trip at 2.7 v. to detect vdd drop at 2.7 v, an external circuit or device such as the wire lessusb lp - cyrf6936 must be employed; or if the design permits, the nearest lvd trip value at 2.9 v can be used. 3.60 v 3.00 v 93 khz 12 mhz cpu frequency vdd voltage 2.40 v 3 mhz valid operating region 2.70 v 3.00 v 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 v 6 mhz 2.40 v slimo mode=1 slimo mode=1 slimo mode=1 slimo mode=0 [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 16 of 39 absolute maximum ratings operating temperature table 7. absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?40 ? +90 c higher storage temperatures reduce data retention time. t baketemp bake temperature 125 see package label c t baketime bake time see package label 72 hours t a ambient temperature with power applied 0 ? +70 c vdd supply voltage on vdd relative to vss ?0.5 ? 5 v v io dc input voltage vss ? 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss ? 0.5 ? vdd + 0.5 v i mio maximum current in to any port pin ?25 ? +25 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 8. operating temperature parameter description min typ max unit notes t a ambient temperature 0 ? +70 c t j junction temperature 0 ? +85 c the temperature rise from ambient to junction is package specific. see table 31 on page 30 . the user must limit the power consumption to comply with this requirement. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 17 of 39 dc electrical characteristics dc chip-level specifications ta b l e 9 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. dc gpio specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 9. dc chip-level specifications parameter description min typ max unit notes vdd supply voltage 2.40 ? 3.6 v see table 16 on page 20 . i dd3 supply current, imo = 6 mhz using slimo mode. ? 1.2 2 ma conditions are vdd = 3.3 v, t a = 25 c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i dd27 supply current, imo = 6 mhz using slimo mode. ? 1.1 1.5 ma conditions are vdd = 2.55 v, t a = 25 c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4. ? a vdd = 2.55 v, 0 c < ? t a < 40 c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 ? a vdd = 3.3 v, 0 c < ? t a < 70 c. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0 v to 3.6 v. v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate vdd. vdd = 2.4 v to 3.0 v. agnd analog ground v ref ? 0.003 v ref v ref + 0.003 v table 10. 3.3 v dc gpio specifications parameter description min typ max unit notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level vdd ? 1.0 ?? vi oh = 3 ma, v dd > 3.0 v v ol low output level ? ? 0.75 v i ol = 10 ma, v dd > 3.0 v i oh high level source current 3 ? ? ma i ol low level sink current 10 ? ? ma v il input low level ? ? 0.8 v vdd = 3.0 to 3.6. v ih input high level 2.1 ? v vdd = 3.0 to 3.6. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 18 of 39 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 11. 2.7v dc gpio specifications parameter description min typ max unit notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level vdd ? 0.4 ?? vi oh = 2.5 ma (6.25 typ), v dd = 2.4 to 3.0 v (16 ma maximum, 50 ma typ combined i oh budget). v ol low output level ? ? 0.75 v i ol = 10 ma, v dd = 2.4 to 3.0 v (90 ma maximum combined i ol budget). i oh high level source current 2.5 ? ? ma i ol low level sink current 10 ? ? ma v il input low level ? ? 0.75 v vdd = 2.4 to 3.0. v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0. v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . table 12. 3.3-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ ? c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a i eboa00 input leakage current (port 0, pin 0 analog pin) ? 50 ? na gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 ? c v cmoa common mode voltage range 0 ? v dd ? 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 13. 2.7-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ ? c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a i eboa00 input leakage current (port 0, pin 0 analog pin) ? 50 ? na gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 ? c v cmoa common mode voltage range 0 ? v dd ? 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 19 of 39 dc switch mode pump specifications ta b l e 1 4 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 14. dc switch mode pump (smp) specifications parameter description min typ max unit notes v pump3v 3.3 v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. [2] average, neglecting ripple. smp trip voltage is set to 3.25 v. v pump2v 2.6 v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. [2] average, neglecting ripple. smp trip voltage is set to 2.55 v. i pump available output current v bat = 1.5 v, v pump = 3.25 v v bat = 1.3 v, v pump = 2.55 v 8 8 ? ? ? ? ma ma configuration of footnote. [2] smp trip voltage is set to 3.25 v. smp trip voltage is set to 2.55 v. v bat3v input voltage range from battery 1 .0 ? 3.3 v configuration of footnote. [2] smp trip voltage is set to 3.25 v. v bat2v input voltage range from vattery 1. 0 ? 2.8 v configuration of footnote. [2] smp trip voltage is set to 2.55 v. v batstart minimum input voltage from vattery to start pump 1.2 ? ? v configuration of footnote. [2] 0 c < t a < 100 c. 1.25 v at t a = ?40 c. ? v pump_line line regulation (over vi range) ? 5 ? %v o configuration of footnote. [2] v o is the vdd value for pump trip specified by the vm[2:0] setting in the dc por and lvd specification, table 16 on page 20 . ? v pump_load load regulation ? 5 ? %v o configuration of footnote. [2] v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 16 on page 20 . ? v pump_ripple output vovltage ripple (depends on cap/load) ? 100 ? mvpp configuration of footnote. [2] load is 5 ma. e 3 efficiency 35 50 ? % configuration of footnote. [2] load is 5 ma. smp trip voltage is set to 3.25 v. e 2 efficiency 35 80 ? % for i load = 1 ma, v pump = 2.55 v, v bat = 1.3 v, 10 ? h inductor, 1 ? f capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % note 2. l 1 = 2 ? h inductor, c 1 = 10 ? f capacitor, d 1 = schottky diode. see figure 12 on page 20 . [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 20 of 39 figure 12. basic switch mode pump circuit dc analog mux bus specifications ta b l e 1 5 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 1 6 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. battery c 1 d 1 + encore iii lv vdd vss smp v bat l 1 v pump table 15. dc analog mux bus specifications parameter description min typ max unit notes r sw switch resistance to common analog bus ? ? 400 800 ? ? vdd > 2.7 v 2.4 v < ? vdd < ? 2.7 v r vdd resistance of initialization switch to vdd ? ? 800 ? table 16. dc por and lvd specifications parameter description min typ max unit notes v ppor0 v ppor1 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b ? 2.36 2.82 2.40 2.95 v v vdd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. vdd value for lvd trip v lvd0 vm[2:0] = 000b 2.40 2.45 2.51 [3] v v lvd1 vm[2:0] = 001b 2.85 2.92 2.99 [4] v v lvd2 vm[2:0] = 010b 2.95 3.02 3.09 v v lvd37 vm[2:0] = 011b 3.06 3.13 3.20 v vdd value for pump trip v pump0 vm[2:0] = 000b 2.45 2.55 2.62 [5] v v pump1 vm[2:0] = 001b 2.96 3.02 3.09 v v pump2 vm[2:0] = 010b 3.03 3.10 3.16 v v pump3 vm[2:0] = 011b 3.18 3.25 3.32 [6] v notes 3. always greater than 50 mv above vppor (porlev = 00) for falling supply. 4. always greater than 50 mv above vppor (porlev = 01) for falling supply. 5. always greater than 50 mv above vlvd0. 6. always greater than 50 mv above vlvd3. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 21 of 39 dc programming specifications ta b l e 1 7 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. dc i 2 c specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 17. dc programming specifications parameter description min typ max unit notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional requirements of external programmer tools. v ddlv low v dd for verify 2.4 2.5 2.6 v this specification applies to the functional requirements of external programmer tools. v ddhv high v dd for verify 3.5 3.6 3.7 v this specification applies to the functional requirements of external programmer tools. v ddiwrite supply voltage for flash write operation 2.7 ? 3.6 v this specification applies to this device when it is executing internal flash writes. i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd ? 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 [7] ? ? ? erase/write cycles per block. flash ent flash dndurance (total) [8] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years table 18. dc i 2 c specifications [9] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v ?? v dd ?? 3.6 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v ?? v dd ?? 3.6 v notes 7. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. voltag e ranges are 2.4 v to 3.0 v and 3.0 v to 3.6 v. 8. a maximum of 36 x 50,000 block endurance cycles is allowed. th is may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 ma ximum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). 9. all gpio meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 22 of 39 ac electrical characteristics ac chip-level specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 19. 3.3 v ac chip-level specifications parameter description min typ max unit notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 [10, 11] mhz trimmed for 3.3 v operation using factory trim values. see figure 11 on page 15 . slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [10, 11] mhz trimmed for 3.3 v operation using factory trim values. see figure 11 on page 15 . slimo mode = 1. f cpu2 cpu frequency (3.3 v nominal) 0.093 12 12.3 [10, 11] mhz slimo mode = 0. f blk33 digital block frequency (3.3 v nominal) 0 24 24.6 [10, 12] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k_u internal low speed oscillator untrimmed frequency 5 ? 100 khz dc ilo internal low speed oscillator duty cycle 20 50 80 % t xrst external reset pulse width 10 ? ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [11] mhz trimmed. using factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v / ms t powerup time from end of por to cpu executing code ? 16 100 ms t jit_imo 24-mhz imo cycle-to- cycle jitter (rms) [13] ? 200 700 ps 24-mhz imo long term n cycle-to-cycle jitter (rms) [13] ? 300 900 ps n = 32 24-mhz imo period jitter (rms) [13] ? 100 400 ps notes 10. accuracy derived from internal main oscillator with appropriate trim for vdd range. 11. 3.0 v < vdd < 3.6 v. 12. see the individual user module data sheets for information on maximum frequencies for user modules. 13. refer to cypress jitter specifications application note an5054 ?understanding datasheet jitter specifications for cypress timing products? at www.cypress.com under application notes for more information. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 23 of 39 table 20. 2.7 v ac chip-level specifications parameter description min typ max unit notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 0 12.7 [14, 15] mhz trimmed for 2.7 v operation using factory trim values. see figure 11 on page 15 . slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [14, 15] mhz trimmed for 2.7 v operation using factory trim values. see figure 11 on page 15 . slimo mode = 1. f cpu1 cpu frequency (2.7 v nominal) 0.093 3 3.15 [14, 15] mhz 12 mhz only for slimo mode = 0. f blk27 digital block frequency (2.7 v nominal) 0 12 12.5 [14, 15] mhz refer to the ac digital block specifications. f 32k1 internal low speed oscillator frequency 8 32 96 khz f 32k_u internal low speed oscillator untrimmed frequency 5 ? 100 khz dc ilo internal low speed oscillator duty cycle 20 50 80 % t xrst external reset pulse width 10 ? ? ? s f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v / ms t powerup time from end of por to cpu executing code ? 16 100 ms t jit_imo 12 mhz imo cycle-to-cycle jitter (rms) [16] ? 400 1000 ps 12 mhz imo long term n cycle-to-cycle jitter (rms) [16] ? 600 1300 ps n = 32 12 mhz imo period jitter (rms) [16] ? 100 500 ps notes 14. accuracy derived from internal main oscillator with appropriate trim for vdd range. 15. 2.4 v < vdd < 3.0 v. 16. refer to cypress jitter sp ecifications application note an5054 ?understanding datasheet jitter specifications for cypress timing products? at www.cypress.com under application notes for more information. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 24 of 39 ac gpio specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. figure 13. gpio timing diagram ac operational amplifier specifications ta b l e 2 3 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7v at 25 c and are for design guidance only. table 21. 3.3 v ac gpio specifications parameter description min typ max unit notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 3.6 v, 10%?90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 3.6 v, 10%?90% table 22. 2.7 v ac gpio specifications parameter description min typ max unit notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0 v, 10%?90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0 v , 10%?90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0 v, 10%?90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0 v, 10%?90% tfallf tfalls trisef tr is es 90% 10% gpio pin output voltage table 23. ac operational amplifier specifications parameter description min typ max unit notes t comp comparator mode response time, 50 mv overdrive 100 200 ns ns vdd > 3.0 v. 2.4 v < vcc < ? 3.0 v. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 25 of 39 ac digital block specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 24. 3.3 v ac digital block specifications function description min typ max unit notes all functions block input clock frequency ? ? 24.6 mhz 3.0 v < vdd < 3.6 v. timer/ counter/ pwm enable input pulse width 50 [17] ? ? ns input clock frequency ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns input clock frequency ? ? 24.6 mhz 3.0 v ? vdd ? 3.6 v. spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock frequency ? ? 4.1 mhz note for spis input clock frequency: the input clock is the spi sclk in spis mode. width of ss_ negated between transmissions 50 ? ? ns transmitter input clock frequency ? ? 24.6 mhz the baud rate is equal to the input clock frequency divided by 8. receiver input clock frequency ? ? 24.6 mhz the baud rate is equal to the input clock frequency divided by 8. table 25. 2.7 v ac digital block specifications function description min typ max unit notes all functions block input clock frequency ? ? 12.7 mhz 2.4 v ? vdd ? 3.0 v. timer/ counter/ pwm enable input clock width 100 ? ? ns input clock frequency ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns input clock frequency ? ? 12.7 mhz 2.4 v ? vdd ?? 3.0 v. spim input clock frequency ? ? 6.35 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock frequency ? ? 4.1 mhz note for input clock frequency: the input clock is the spi sclk in spis mode. width of ss_ negated between transmissions 100 ? ? ns transmitter input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. receiver input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. note 17. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 26 of 39 ac external clock specifications the following tables list guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. ac programming specifications ta b l e 2 8 lists guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 3.0 v to 3.6 v and 0 c< t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 26. 3.3 v ac external clock specifications parameter description min typ max unit notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ? ? s table 27. 2.7 v ac external clock specifications parameter description min typ max unit notes f oscext frequency with cpu clock divide by 1 0.093 ?3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power-up imo to switch 150 ? ? ? s table 28. ac programming specifications parameter description min typ max unit notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? vdd ? 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 ? vdd ? 3.0 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once. t program_ hot flash block erase + flash block write time ? ? 100 ms 0 c ? t j ? 100 c t program_ cold flash block erase + flash block write time ? ? 200 ms -40 c ? t j ? 0 c [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 27 of 39 ac i 2 c specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 3.6 v and 0 c < t a < 70 c, or 2.4 v to 3.0 v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 29. ac characteristics of the i 2 c sda and scl pins for vdd > ? 3.0 v parameter description standard-mode fast-mode unit min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c set up time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data setup time 250 ?100 [18] ?ns t sustoi2c set up time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns note 18. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but th e requirement t su;dat > 250 ns must then be met. this is automatically the case if the device does not stretch the low peri od of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. table 30. 2.7 v ac characteristics of the i 2 c sda and scl pins (f ast-mode not supported) parameter description standard-mode fast-mode unit min max min max f scli2c scl clock frequency 0 100 ??khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? ? s t sustai2c setup time for a repeated start condition 4.7 ? ? ? ? s t hddati2c data hold time 0 ? ? ? ? s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?? ?ns [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 28 of 39 figure 14. definition of timing for fast-/standard-mode on the i 2 c bus packaging information this section illustrates the packaging specifications for the cy 7c603xx device, along with the thermal impedances for each pack age. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the do cument titled psoc emulator pod dimensions at http://www.cypress.com . packaging dimensions figure 15. 28-pin (210-mil) ssop i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition 51-85079 *d [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 29 of 39 figure 16. 32-pin qfn (5 5 mm) (sawn) 001-30999 *c [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 30 of 39 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 31. thermal impedances per package package typical ? ja [19] typical ? jc 28 ssop 96 c / w 39 c / w 32 qfn [21] 22 c / w 12 c / w table 32. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28 ssop 260 c 20 s 32 qfn 260 c 20 s notes 19. t j = t a + power x ? ja 20. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with s n-pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications. 21. to achieve the thermal impedance specified for the qfn package, re fer to "application notes for su rface mount assembly of amkor 's microlead- frame (mlf) packages" available at http://www.amkor.com . [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 31 of 39 ordering information the following table lists the cy7c603xx device?s key package features and ordering codes ordering code definitions table 33. cy7c603xx device key features and ordering information package type ordering part number flash size ram size smp i/o 28-ssop cy7c60323-pvxc 8k 512 no 24 28-ssop tape and reel cy7c60323-pvxct 8k 512 no 24 32-qfn sawn cy7c60323-ltxc 8k 512 no 28 32-qfn sawn tape and reel CY7C60323-LTXCT 8k 512 no 28 32-qfn sawn cy7c60333-ltxc 8k 512 yes 26 32-qfn sawn tape and reel cy7c60333-ltxct 8k 512 yes 26 cy 7 c technology: cmos cypress products company id : cy = cypress 60 family name: low voltage rf companion mcu part number: 1xx, 2xx = encore ii lv; 3xx = encore iii lv; 4xx = encore iv lv xxx [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 32 of 39 acronyms acronyms used ta b l e 3 4 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x 66, cy8c27x43, cy8c24x94, cy8c24x23 , cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 34. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter pcb printed circuit board api application programming interface pga programmable gain amplifier cpu central processing unit pll phase-locked loop ct continuous time por power on reset dac digital-to-analog converter ppor precision power on reset dc direct current psoc ? programmable system-on-chip dtmf dual-tone multi-frequency pwm pulse width modulator eco external crystal oscillator qfn quad flat no leads eeprom electrically erasable programmable read-only memory rtc real time clock gpio general purpose i/o sar successive approximation ice in-circuit emulator sc switched capacitor ide integrated development environment slimo slow imo ilo internal low speed oscillator smp switch-mode pump imo internal main oscillator spi tm serial peripheral interface i/o input/output sram static random access memory issp in-system serial programming srom supervisory read only memory lcd liquid crystal display ssop s hrink small-outline package lpc low power comparator usb universal serial bus lvd low voltage detect wdt watchdog timer mac multiply-accumulate xres external reset [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 33 of 39 document conventions units of measure ta b l e 3 5 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercas e with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pr efix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 35. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes h microhenry db decibels s microsecond c degree celsius ms millisecond f microfarad ns nanosecond ff femto farad ps picosecond pf picofarad v microvolts khz kilohertz mv millivolts mhz megahertz mvpp millivolts peak-to-peak rt-hz root hertz nv nanovolts k ? kilohm v volts ? ohm w microwatts a microampere w watt ma milliampere mm millimeter na nanoampere ppm parts per million pa pikoampere % percent glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opam p circuits. these are sc (switched capa citor) and ct (continuous time) blocks. these blocks can be interconn ected to provide adcs, dacs , multi-pole filt ers, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interfac e between a computer applicat ion and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for prog rammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the posit ive temperature coefficient of vt with the negative temperature coefficient of vbe, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amp lifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as , for example, full width at half maximum. [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 34 of 39 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field ) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved fo r io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to r oute nets with similar routing patterns. 2. a set of signals performing a common function and carry ing similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is cont rolled by a piezoelectric crystal. typically a piezoelectric crys tal is less sensitive to ambient temperatur e than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communic ations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic bl ocks that can act as a counter, timer, serial receiver, serial transm itter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital (adc) converter performs the reverse operation. glossary (continued) [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 35 of 39 duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc devi ce. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volati le technology that provides users with the programmability and data storage of eproms, plus in-system erasability. non- volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it wa s later used as a simple internal bus system for building control electronics. i2c uses only two bi-directional pins, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer progra m, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code exec ution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning t he device to the point in the program w here it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses vdd and provides an interrupt to the system when vdd falls below a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exch anges between two devices. or when devices are cascaded in width, the master device is the one that controls th e timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . glossary (continued) [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 36 of 39 microcontroller an integrated circuit chip that is designed pr imarily for control systems and products. in addition to a cpu, a microcontroller typically include s memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minima l quantity of chips, thus achieving ma ximal possible miniaturization. this in turn, reduces the volume and the cost of the cont roller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the volta ge is below a pre-set level. th is is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and progra mmable system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. glossary (continued) [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 37 of 39 shift register a memory storage dev ice that sequentially shifts a wo rd either left or right to ou tput a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external inte rface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged until it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (hig h-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modu les also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. register s in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued) [+] feedback
cy7c603xx document number: 38-16018 rev. *l page 38 of 39 document history page description title: cy7c603xx, encore? iii low voltage document number: 38-16018 rev. ecn no. orig. of change submission date description of change ** 339394 bon see ecn new advance data sheet. *a 399556 bha see ecn changed from advance information to preliminary. changed data sheet format. removed cy7c604xx. *b 461240 tyj see ecn modified figure 10 to include 2.7 v vdd at 12 mhz operation. *c 470485 tyj see ecn corrected part numbers in secti on 4 to match with part numbers in ordering infor- mation. from cy7c60323-28pvxc, cy7c60323-56lfxc and cy7c60333-56lfxc to cy7c60323-pvxc, cy7c60323-lfxc and cy7c60333-lfxc respectively. changed from preliminary to final data sheet. *d 513713 kkvtmp see ecn change title from wireless encore ii to encore iii low voltage. applied new template formatting. *e 2197567 uvs/aesa see ecn a dded 32-pin sawn qfn pin diagram , package diagra m, and ordering information. *f 2620679 cmcc/pyr s 12/12/2008 added packaging handling information. deleted note regarding link to amkor.com for mlf package dimensions. *g 2852393 xut 01/15/2010 added table of contents . updated dc gpio, ac chip-level, and ac programming specifications as follows: replaced tramp (time) with srpowe r_up (slew rate) specification. added i oh , i ol , dcilo, f32k_u, tp owerup, teraseall, tprogram_hot, and tprogram_cold specifications. updated copyright and sales, solutions, and legal information urls. updated 28-pin ssop and 32-pin qfn (punch and sawn) package diagrams. *h 2892683 njf 03/15/2010 updated cypress website links. updated development kits . updated 3.3 v ac chip-level specifications and 2.7 v ac chip-level specifica- tions . removed ac analog mux bus specs section. updated 32-pin sawn qfn package diagram. removed inactive parts from ordering information . *i 2911952 gnkk 04/13/2010 updated revision in the footer. *j 3014656 bha 09/15/2010 updated logic block diagram to encore iii lv. added ordering code definitions added acronyms and units of measure table. datasheet updated as per latest template. *k 3114976 njf 12/19/10 updated 3.3-v and 2.7-v ac digital block specifications. updated dc operational amplifier specifications. updated i 2 c timing diagram. added dc i 2 c specifications. added uilo max limit. added tjit_imo specific ation, removed existing jitter specifications. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. *l 3180466 csai 02/23/2011 updated packaging information . updated in new template. [+] feedback
document number: 38-16018 rev. *l revised february 23, 2011 page 39 of 39 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c603xx ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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